timing problem

Hi everyone ：

Timequest shows errors, removal slack：

http://www.alteraforum.com/forum/attachment.php?attachmentid=9466&stc=1

The timing report is ：

http://www.alteraforum.com/forum/attachment.php?attachmentid=9467&stc=1

In the report timing, the from clock is one output of my pll in Qsys (I think this is the launch clk), the to clock is the clk of fpga, the input of pll(I think this is the latch clk)

http://www.alteraforum.com/forum/attachment.php?attachmentid=9468&stc=1

From the report timing waveform, it shows that the data arrival is 0.854ns earlier than the data required time, so I think if I add 2ns phase delay to the pll’s output, the problem will be fixed.

Then I add 2ns phase delay to the pll’s output in the Qsys, generate the system, then start compilation in the quartus.

Then I check the timequest, and I find the problems still there, even the waveform of the report timing never changes.

I dout that the quartus did not change the settings of the pll.

Am I right?

How to fix it?

Thanks!