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hi thanks !
i am new to timing problems, can you explain more?
or can you give me a document?
thanks!
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Not a lucky start for a beginner as this is a bit hard.
reset whether applied to async port or through D input(called synchronous) must be presynchronised by two stage register. This path itself need be excluded from timing.
If reset is not registred then TQ will not report as there would be no reg to reg path and this is misleading. In your case you have TQ reporting it but with failure and hence your reset is registered somewhere...
if double synchroniser does not work then it could be helped by applying further registers on reset path to reduce the fanout or duplicate it and don't let compiler remove them.
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