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Altera_Forum's avatar
Altera_Forum
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20 years ago

Tightlycoupled instr memories and JTAG debug

Hi all,

Just a silly question: I am designing a multiprocessor system, and I would like to use only tightly coupled memories on one cpu.

I added a CPU, with a tightly coupled instruction master (i0), 2 tightly coupled data master (s0 and s1), and a data master.

Then I have a dual port onchip rom, connected to i0 and s0

Then I have an onchip ram connected to s1

Then I get the following warning:

"Break location slave cpu_2/jtag_debug_module is not mastered by an instruction master of cpu_2"

The problem I think is that there is no instruction cache, that implies that there is not an avalon instruction master that can be connected to the jtag module.

If I add an instruction master (adding e.g. 512 bytes of instruction cache), the warning goes away.

Question: Is that warning a problem?

bye

PJ

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    I discovered that this warning message is noted in the Nios II v5.0 erratta ( http://www.altera.com/support/ip/processor...50-er.html#core (http://www.altera.com/support/ip/processors/nios2/ips-niosii-50-er.html#core) )

    "Reset address in TCM with no other instruction master memory causes false warning

    Placing program memory (.text) and data memory (.rodata and .rwdata, etc) in a dual port memory in which only instruction masters are connected to one port and only data masters of the same CPU are connected to the other port is not supported. A typical case where this might be done would be a dual port memory with one port connected to a trellis coded modulation (TCM) instruction master and the other port connected to a TCM data master. This configration is not supported.

    Workaround: Do not place program memory (.text) and data memory (.rodata and .rwdata, etc.) in a dual port memory in which only instruction masters are connected to one port and only data masters are connected."
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    You are correct that you need an instruction cache (and the associated instruction master) if you want the debug core.

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    After reading your post I have a question:

    "2 tightly coupled data master (s0 and s1)" do you mean you dual ported an onchip memory then hooked up to two tightly coupled masters or did you mean d0 and d1?

    The reason why this caught my eye was because you meantioned a multiple CPU system. If you are sharing this memory keep data corruption in the back of your mind (if both masters can access it then you may cause a problem depending on how you use it).
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Hi BadOmen,

    <div class='quotetop'>QUOTE </div>

    --- Quote Start ---

    "2 tightly coupled data master (s0 and s1)" do you mean you dual ported an onchip memory then hooked up to two tightly coupled masters or did you mean d0 and d1?[/b]

    --- Quote End ---

    I dual-ported the onchip-rom, putting a tightly coupled instruction master on one side and a tightly coupled data master on the other. I think I need that to let the CPU read the content of the onchip rom... is that right?

    Then I have a ram onchip memory for the local data of the CPU

    The idea is that I wanted to get the best performace from an onchip nios II.

    Finally, I used another normal avalon data master to connect to another onchip memory used to exchange data together with other 2 CPUs.

    <div class='quotetop'>QUOTE </div>

    --- Quote Start ---

    The reason why this caught my eye was because you meantioned a multiple CPU system. If you are sharing this memory keep data corruption in the back of your mind (if both masters can access it then you may cause a problem depending on how you use it).[/b]

    --- Quote End ---

    I know, that&#39;s the part of the game I enjoy the best :-)

    bye

    PJ