Tightlycoupled instr memories and JTAG debug

Hi BadOmen,

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"2 tightly coupled data master (s0 and s1)" do you mean you dual ported an onchip memory then hooked up to two tightly coupled masters or did you mean d0 and d1?[/b]

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I dual-ported the onchip-rom, putting a tightly coupled instruction master on one side and a tightly coupled data master on the other. I think I need that to let the CPU read the content of the onchip rom... is that right?

Then I have a ram onchip memory for the local data of the CPU

The idea is that I wanted to get the best performace from an onchip nios II.

Finally, I used another normal avalon data master to connect to another onchip memory used to exchange data together with other 2 CPUs.

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The reason why this caught my eye was because you meantioned a multiple CPU system. If you are sharing this memory keep data corruption in the back of your mind (if both masters can access it then you may cause a problem depending on how you use it).[/b]

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I know, that&#39;s the part of the game I enjoy the best :-)

bye

PJ