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Altera_Forum
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20 years ago

Tightlycoupled instr memories and JTAG debug

Hi all, Just a silly question: I am designing a multiprocessor system, and I would like to use only tightly coupled memories on one cpu. I added a CPU, with a tightly coupled instruction m...
Altera_Forum's avatar
Altera_Forum
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20 years ago

You are correct that you need an instruction cache (and the associated instruction master) if you want the debug core.