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Altera_Forum
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20 years ago

Tightlycoupled instr memories and JTAG debug

Hi all, Just a silly question: I am designing a multiprocessor system, and I would like to use only tightly coupled memories on one cpu. I added a CPU, with a tightly coupled instruction m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

After reading your post I have a question:

"2 tightly coupled data master (s0 and s1)" do you mean you dual ported an onchip memory then hooked up to two tightly coupled masters or did you mean d0 and d1?

The reason why this caught my eye was because you meantioned a multiple CPU system. If you are sharing this memory keep data corruption in the back of your mind (if both masters can access it then you may cause a problem depending on how you use it).