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Altera_Forum
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19 years ago

THE WM8731 ON DE2

THE WM8731 ON DE2

serial data from digital audio interface

I want to make "serial data", which is out of digital audio interface after AD sampling in WM8731,into the 16bit "parallel data",which will be stored in the SRAM on theED2 board.

So I want to ask what should I do? Are there some module programme available?

Some days ago, I have write a verilog programme for serial-to-parallel conversion.But, the result of function simulation is not correct.

ps:1.AD sampling rate is 8KHZ

2.ADCDAT is 16 bit

3.NORMAL mode

4.digital audio interface format is I2S.

5.programme I have write as follow:

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    ///////////////////////////////////////////////////////////////////////

    //when AUD_ADCLRC==0, do 16bit serial-to-parallel.this module is only//

    //for leftchannel AUD_ADCDAT data. //

    ///////////////////////////////////////////////////////////////////////

    module leftchannel(clk,reset,AUD_ADCLRC_n,AUD_ADCDAT,pDATAOut,en);

    input clk; //connect BCLK, module time

    input reset; //

    input AUD_ADCLRC_n;

    input AUD_ADCDAT; //serial data from digital audio interface

    output[15:0] pDATAOut; //parallel

    output en; // enable output

    wire clk;

    wire reset;

    wire AUD_ADCLRC_n;

    wire AUD_ADCDAT;

    reg en;

    reg [15:0] pDATAOut;

    reg [15:0] pDATAOut_temp;

    reg [5:0] counter ; //counter for state S2

    reg [8:0] counter0; //counter for state S3

    reg [1:0] state; //

    parameter S0=2'b00, //

    S1=2'b01, //

    S2=2'b11, //

    S3=2'b10; //

    always @(negedge reset or negedge clk)

    begin

    if (!reset)

    begin

    state <= S0; //

    //counter <= 5&#39;b00000;

    //counter0 <= 8&#39;b0000_0000;

    end

    else

    begin

    case(state) //

    S0:

    begin

    if (AUD_ADCLRC_n == 1)

    state <= S0; //

    else

    state <= S1;

    end

    S1:

    begin

    state <= S2;

    end

    S2:

    begin

    if (counter == 5&#39;b10000)

    state <= S3;

    else

    state <= S2;

    end

    S3:

    begin

    if (counter == 8&#39;b1010_1111)

    state <= S0;

    else

    state <= S3;

    end

    endcase

    end

    end

    always @ (negedge clk) // (state)

    begin

    case(state)

    S0:

    begin

    pDATAOut_temp <= 4&#39;h0000;

    en <= 1&#39;b0;

    counter <= 5&#39;b00000;

    counter0 <= 8&#39;b0000_0000;

    end

    S1:

    begin

    pDATAOut_temp <= 4&#39;h0000;

    en <= 1&#39;b0;

    counter <= 5&#39;b00000;

    counter0 <= 8&#39;b0000_0000;

    end

    S2:

    begin

    en <= 1&#39;b0;

    case(counter)

    5&#39;b00000:

    begin

    pDATAOut_temp[15] <= AUD_ADCDAT;

    counter <= counter+5&#39;b00001;

    end

    5&#39;b00001:

    begin

    pDATAOut_temp[14] <= AUD_ADCDAT;

    counter <= counter+5&#39;b00001;

    end

    .

    .

    .

    5&#39;b01111:

    begin

    pDATAOut_temp[0] <= AUD_ADCDAT;

    counter <= counter+5&#39;b00001;

    end

    default:

    counter <= counter+5&#39;b00001;

    endcase

    end

    S3:

    begin

    //if (counter0 == 8&#39;b0000_0000)

    begin

    en <= 1&#39;b1;

    pDATAOut <= pDATAOut_temp;

    counter0 <= counter0+8&#39;b0000_0001;

    end

    //else

    //begin

    //en <= 1&#39;b0;

    // pDATAOut_temp <= 4&#39;h0000;

    // pDATAOut <= 4&#39;h0000;

    //counter0 <= counter0+8&#39;b0000_0001;

    //end

    end

    endcase

    end

    endmodule