The Highest Carrier Frequency for Stratix III

For example parts that can be used to modulate your 100MHz signal, check out this previous discussion between Kaz and myself;

http://www.alteraforum.com/forum/showthread.php?t=29701&page=2

Cheers,

Dave

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Sure its practical.

I have ~600 Stratix II FPGAs synchronously processing 4GHz of sampled bandwidth across 120 boards, and another ~1000 FLEX10KE FPGAs (yeah, that old) processing another 8GHz (all using 1GHz clock rate ADCs and parallel processing);

Dave

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Hi Dave

You may be focussed on research based work. In all the companies I worked for, we never went down anything more than one level of parallel processing of dsp path. I doubt even experienced engineer can easily manage a simple fir filter on even/odd signal paths let alone breaking signal path down further. In a commercial environment for high speed there are far better solutions than fpgas which are mainly used to lift up baseband a bit higher than dc.

I think the post by Mohanadig suggests he is too fresh for parallel work.

I already have the part of mixing the signal with the 3GHz solved I had the output from the two HSMC outputs.

but, I didn't really get what you mentioned about converting to analog signal first .. because the case is to have the up converted signal inside the FPGA before it is sent to the HSMC output.

Thanks,

Hi Kaz,

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In all the companies I worked for, we never went down anything more than one level of parallel processing of dsp path. I doubt even experienced engineer can easily manage a simple fir filter on even/odd signal paths let alone breaking signal path down further. In a commercial environment for high speed there are far better solutions than fpgas which are mainly used to lift up baseband a bit higher than dc.

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Yeah, fair enough :)

Cheers,

Dave

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I already have the part of mixing the signal with the 3GHz solved I had the output from the two HSMC outputs.

but, I didn't really get what you mentioned about converting to analog signal first .. because the case is to have the up converted signal inside the FPGA before it is sent to the HSMC output.

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The signals on the HSMC outputs are digital values.

Is your 3GHz mixing logic digital (like one of the devices in the links above), or analog?

If the mixing is analog, then you would need an digital-to-analog conversion (DAC) of your 100MHz bandwidth signal, where the 100MHz bandwidth signal is possibly resampled to a 500MHz clock rate, or 1GHz clock rate signal, prior to analog mixing.

Cheers,

Dave

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It is analog, and I will put that in my consideration thanks for the help.

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Ok, so you will have to convert your 100MHz bandwidth HSMC data to analog.

Texas Instruments is now making their ADC/DAC boards with HSMC interfaces, eg.,

http://focus.ti.com/docs/toolsw/folders/print/dac3484evm.html

I haven't used this part, but it looks like it has the features you would need.

Cheers,

Dave