The Highest Carrier Frequency for Stratix III

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Sure its practical.

I have ~600 Stratix II FPGAs synchronously processing 4GHz of sampled bandwidth across 120 boards, and another ~1000 FLEX10KE FPGAs (yeah, that old) processing another 8GHz (all using 1GHz clock rate ADCs and parallel processing);

Dave

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Hi Dave

You may be focussed on research based work. In all the companies I worked for, we never went down anything more than one level of parallel processing of dsp path. I doubt even experienced engineer can easily manage a simple fir filter on even/odd signal paths let alone breaking signal path down further. In a commercial environment for high speed there are far better solutions than fpgas which are mainly used to lift up baseband a bit higher than dc.

I think the post by Mohanadig suggests he is too fresh for parallel work.