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Altera_Forum's avatar
Altera_Forum
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19 years ago

System not generating with 2 clock sources

Hi folks,

I am having a problem when trying to use two PLL’s on my Cyclone II EP2C35in SOPC builder. I have one 100MHz PLL derived from a 50 MHz oscillator and another 10Mhz PLL derived from the 50 MHz oscillator. I want my processor etc to run at 100Mhz and some counters I am using to run at 10MHz. If I generate my system using either 100Mhz or 10Mhz PLL’s to drive the counters and processor, all is fine. If however I change the counters to run from the 10Mhz PLL I get the following errors in generation.

# 2006.10.03 15:15:53 (*) Running Generator Program for pll_0# 2006.10.03 15:15:55 (*) Running Generator Program for counter_zero_0# 2006.10.03 15:15:58 (*) Running Generator Program for pll_1# 2006.10.03 15:16:00 (*) Running Generator Program for clock_0# 2006.10.03 15:16:02 (*) Running Generator Program for clock_1

ERROR:

c:/altera/quartus60/sopc_builder/components/altera_avalon_clock_adapter/mk_clock_crossing.pl 76 CALLED (e_project::output)

c:/altera/quartus60/sopc_builder/bin/europa/e_project.pm 1510 CALLED (e_module::to_vhdl)

c:/altera/quartus60/sopc_builder/bin/europa/e_module.pm 1918 CALLED (e_module::_vhdl_make_string)

c:/altera/quartus60/sopc_builder/bin/europa/e_module.pm 1677 CALLED (e_module::_tagged_hdl_strings)

c:/altera/quartus60/sopc_builder/bin/europa/e_module.pm 1290 CALLED (e_register::to_vhdl)

c:/altera/quartus60/sopc_builder/bin/europa/e_register.pm 719 CALLED (e_process::to_vhdl)

c:/altera/quartus60/sopc_builder/bin/europa/e_process.pm 634 CALLED (e_if::to_vhdl)

c:/altera/quartus60/sopc_builder/bin/europa/e_if.pm 301 CALLED (e_assign::to_vhdl)

c:/altera/quartus60/sopc_builder/bin/europa/e_assign.pm 602 CALLED (e_expression::to_vhdl)

c:/altera/quartus60/sopc_builder/bin/europa/e_expression.pm 734 CALLED (e_expression::Resize) WHERE

'no width for slave_nativeaddress' OCCURRED on c:/altera/quartus60/sopc_builder/bin/europa/e_expression.pm 2985

Error: Generator program

for module 'clock_1' did NOT run successfully.

generator cmd was 'c:/altera/quartus60//bin/perl561/bin/perl -

Error in processing. System NOT successfully generated.

Highlighted in bold is the 'no width for slave_nativeaddress', I am unsure as to what this is trying to tell me?? When Generating my PLL’s I have used C0 output for 100Mhz PLL and the C1 output for the 10Mhz PLL, is this correct?

Any help appreciated.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Having played about some more with SOPC builder I have noticed that if my counter module is running at a different frequency from the CPU then the system will not generate.

    If I have my counter module and CPU running at 100Mhz, I can run the system ID peripheral, JTAG UART, RAM etc at 10MHz and the system generates correctly. If I try and run the counter at 10Mhz then the system will not generate.

    Has anyone experienced similar problems?
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    --- Quote Start ---

    originally posted by boydal@Oct 4 2006, 09:59 AM

    having played about some more with sopc builder i have noticed that if my counter module is running at a different frequency from the cpu then the system will not generate.

    if i have my counter module and cpu running at 100mhz, i can run the system id peripheral, jtag uart, ram etc at 10mhz and the system generates correctly. if i try and run the counter at 10mhz then the system will not generate.

    has anyone experienced similar problems?

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18544)

    --- quote end ---

    --- Quote End ---

    I have a similar problem, because when generating the SOPC builder system I get the message:

    ------------------------

    ...# 2007.01.11 08:32:23 (*) Running Generator Program for clock_0# 2007.01.11 08:32:26 (*) Running Generator Program for clock_1# 2007.01.11 08:32:29 (*) Running Generator Program for clock_2

    ERROR:

    no width for slave_nativeaddress

    Error: Generator program

    for module &#39;clock_2&#39; did NOT run successfully.

    ...

    ------------------------

    The external input clock is 24 MHz, the first pll has an internal clock output with 25MHz, another with 40MHz and an external clock output with 40MHz. The second pll has an internal clock output with 27MHz, another with 108MHz and an external clock output with 108MHz. The external clock outputs are not used inside the SOPC builder system. Therefore the questions:

    1.) The PLL Megafunction Wizard says &#39;Able to implement the requested PLL&#39;, so why this error?

    2.) Where can I set the width for the slave_nativeaddress?

    @boydal:

    Did you find a solution for your problem? Just changing the Frequency and the system could be generated or what?

    Thanks for any help!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    add an address signal to your VHDL/Verilog module/architecture entity declaration in you components to be imported to SOPC builder. Then when you import your components to SOPC builder map the address signal to the address in the drop downs of the wizard. You do not need to use this address in any way in your VHDL/verilog but it must be present in the arhcitecture/entity/module declaration or it wont generate, hope this helps .

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    --- Quote Start ---

    originally posted by boydal@Jan 11 2007, 10:10 AM

    add an address signal to your vhdl/verilog module/architecture entity declaration in you components to be imported to sopc builder. then when you import your components to sopc builder map the address signal to the address in the drop downs of the wizard. you do not need to use this address in any way in your vhdl/verilog but it must be present in the arhcitecture/entity/module declaration or it wont generate, hope this helps .

    <div align='right'><{post_snapback}> (index.php?act=findpost&pid=20499)

    --- quote end ---

    --- Quote End ---

    Thank you very much, that works perfectly!!!

    At first I could hardly beleive, that this was the problem, but I already realised some time ago, that one of my user_logic modules had a base address and the other one not. I didn&#39;t know why and forgot. Now I also didn&#39;t know what clock_0, ..._1, and so on meant and which clock_xy belonged to which module (I thought it has something to do with the plls). So I didn&#39;t know that these two things went together, thank you very much for that hint!

    And I really don&#39;t need an address in that module, therefore I would have never come to that solution by mistake, so there was no chance for beginners luck http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif