System not generating with 2 clock sources

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originally posted by boydal@Jan 11 2007, 10:10 AM

add an address signal to your vhdl/verilog module/architecture entity declaration in you components to be imported to sopc builder. then when you import your components to sopc builder map the address signal to the address in the drop downs of the wizard. you do not need to use this address in any way in your vhdl/verilog but it must be present in the arhcitecture/entity/module declaration or it wont generate, hope this helps .

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Thank you very much, that works perfectly!!!

At first I could hardly beleive, that this was the problem, but I already realised some time ago, that one of my user_logic modules had a base address and the other one not. I didn&#39;t know why and forgot. Now I also didn&#39;t know what clock_0, ..._1, and so on meant and which clock_xy belonged to which module (I thought it has something to do with the plls). So I didn&#39;t know that these two things went together, thank you very much for that hint!

And I really don&#39;t need an address in that module, therefore I would have never come to that solution by mistake, so there was no chance for beginners luck http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif