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Altera_Forum's avatar
Altera_Forum
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19 years ago

System not generating with 2 clock sources

Hi folks, I am having a problem when trying to use two PLL’s on my Cyclone II EP2C35in SOPC builder. I have one 100MHz PLL derived from a 50 MHz oscillator and another 10Mhz PLL derived from th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

add an address signal to your VHDL/Verilog module/architecture entity declaration in you components to be imported to SOPC builder. Then when you import your components to SOPC builder map the address signal to the address in the drop downs of the wizard. You do not need to use this address in any way in your VHDL/verilog but it must be present in the arhcitecture/entity/module declaration or it wont generate, hope this helps .