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Altera_Forum's avatar
Altera_Forum
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20 years ago

System hangs in reset_device()

Hi,

I'm using a Stratix II development board with NIOS II 1.1 and I am trying to initialize the network interface and the lightweight IP stack as done in the web server example. The network interface is present in my SOPC design.

However, when I initialise the hardware using lwip_devices_init(PRIORITY), it hangs in reset_device():

12 OSIntCtxSw() at \cygdrive\c\altera\kits\nios2\components\altera_nios2\UCOSII\src\os_cpu_a.S:126
11 OS_Sched() at \cygdrive\c\altera\kits\nios2\components\micrium_uc_osii\UCOSII\src\os_core.c:1199
10 OSTimeDly() at \cygdrive\c\altera\kits\nios2\components\micrium_uc_osii\UCOSII\src\os_time.c:55
9 usleep() at \cygdrive\c\altera\kits\nios2\components\altera_nios2\UCOSII\src\alt_usleep.c:90
8 reset_device() at \cygdrive\c\altera\kits\nios2\components\altera_avalon_lan91c111\UCOSII\src\altera_avalon_lan91c111.c:466
7 low_level_init() at \cygdrive\c\altera\kits\nios2\components\altera_avalon_lan91c111\UCOSII\src\altera_avalon_lan91c111.c:753
6 alt_avalon_lan91c111_init() at \cygdrive\c\altera\kits\nios2\components\altera_avalon_lan91c111\UCOSII\src\altera_avalon_lan91c111.c:163
5 netif_add() at \cygdrive\c\altera\kits\nios2\components\altera_lwip\UCOSII\src\downloads\lwip-0.7.2\src\core\netif.c:85
4 lwip_devices_init() at \cygdrive\c\altera\kits\nios2\components\altera_lwip\UCOSII\src\alt_lwip_dev.c:135
3 init_done_func() at ..\SystemInit\Special_c_func.cc:22
2 tcpip_thread() at \cygdrive\c\altera\kits\nios2\components\altera_lwip\UCOSII\src\downloads\lwip-0.7.2\src\api\tcpip.c:92
1 OSStartTsk() at \cygdrive\c\altera\kits\nios2\components\altera_nios2\UCOSII\src\os_cpu_a.S:265

The software initialization appears to complete successfully, but I am stuck at the this point. I have been trying to give different IRQ numbers, to give different priorities to the tasks, reloading the quartus II design many times and resetting the board by taking off the power and waiting for 30 seconds.

Does anyone have an idea would could be going on?

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Yes, I've solved my problems booting both the processor from flash; i.e. setting reset address in flash (each processor at different address...) and using the flash programmer in IDE to download the codes. In this way u control the running of both the processor and then you could also download software directly to SDRAM...

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi Soin,

    all the problems are gone now the reset addresses are set to flash. I haven't tried flashing yet, but I will give that a try today as well. Now it seems to work fine when loading with the Jtag. I use hardware mutexes to synchronise the cpu's , so for now I don't have to worry when one cpu starts earlier then the other.

    Many thanks for all your help!

    Jos