Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSystem Checks fail
Preperations: I followed the usual work flow: Generate Qsys system > Update the Qsys-Block in the Quartus Project >Build Quartus Project > Use Programmer to write the hardware on the FPGA > Gene...
Altera_ForumHonored Contributor
Honored ContributorI FOUND THE PROBLEM:
When there is a timestamp mismatch, this indicates that the "hardware" that was programmed on the FPGA does not match the "hardware" that is attributed in the NIOS project. Somehow the Quartus programmer stored an old path of the hardware's .sof file. Reloading to correct file solved the problem.
