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Altera_Forum's avatar
Altera_Forum
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12 years ago

System Checks fail

Preperations: I followed the usual work flow: Generate Qsys system > Update the Qsys-Block in the Quartus Project >Build Quartus Project > Use Programmer to write the hardware on the FPGA > Gene...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I FOUND THE PROBLEM:

When there is a timestamp mismatch, this indicates that the "hardware" that was programmed on the FPGA does not match the "hardware" that is attributed in the NIOS project.

Somehow the Quartus programmer stored an old path of the hardware's .sof file. Reloading to correct file solved the problem.