Altera_Forum
Honored Contributor
Honored Contributorstill verify failed with on-chip memory??
Hi,
I'm using SratixII 2s60 dev board kit (with two adcs and two dacs on), and I want to run "hello world" in NiosII IDE in debug/release mode. In SOPC I add components of niosIIcore/avalonMMTriBrige/CFIflashcontroller/timer/jtag_uart/onchipmemory, in niosII core I make exception address from onchipmem (offset 0x20) and reset address (offset 0x0) from cfi_flash. Also in NiosII IDE, I choose all programme/stack/heap... mems in on-chip memory, stdout/stdin/stderr in jtag_uart, system clock with timer in sopc, and timestamp timer none. In the run config, I choose jtag device "automatic(the device which has the process"(another choice is EPCS), and NiosII terminal communication device "jtag_uart". when I run the software("hello world"), it fails with "Verify failed between xx and xx", that address is in my on_chip memory, I have read that SDRAM address verify fails quit likely, however even all run in on_chip memory(no sdram at all) still fails with verify fails, so I guess it's either the software(niosII IDE generation) or the non proper configuration in my case. when using debug/release in NIOSII IDE and running in the jtag_uart, what is the relation of : exception address and reset address in NIOSII core configuration in SOPC, programme/stack/heap... memories, flash memory and jtag_uart, even EPCS ??? And any other advices for me ?? I've read about flash_programme user guide, but I'm afraid it's not quit clear to me, last time I used nios2 and quartus is in Y2005/06 , I find a lot changed until now. So please me and make it clearer to me? Thanks, x.p,ma.
