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Altera_Forum
Honored Contributor
Honored ContributorStarting point for DE1 Board
Hi all,
Recently i have buy the Altera DE1 Board. My objectif is to make a projects with Nios II F and all the things with a commented source for everyone want to start a project with DE1 and C code with the Eclipse IDE. After i want to send it to the wiki and here for exemple. I have succesfully integrated and be able to command the Switch , Key and all Led with Nios II Eclipse. if someone already want the project and source tell me. But now i want to add the VGA and i request some help. so just two question please , i know this forum have several VGA question but i just want to make one starting point project for beginner guys ( like me) who want to start a project. 1) Is it Possible to command the VGA directly with the Nios and Eclipse ( by command the Buffer). 2) I have found the Altera Source Code for the CycloneII_2C35 with the VGA. i have added in my SOPC the vga controller and the vid_pll for the 40Mhz clock and 800*600 resolution. i can sucessfuly compile my project in Quartus II and Eclipse too but when i flash it i have no signal in my VGA monitor even with Run as Hardware. Here is my project and my source code , can you tell where is the error ? http://sega4ever.power-heberg.com/fpga/de1_nios.rar Thanks a lot !15 Replies
Altera_ForumIt's still not correct.
Here, replace this section of your code:
with this:system_0 u0 ( // 1) global signals: .clk(CPU_CLK), .reset_n(CPU_RESET), // the_KEY .in_port_to_the_KEY(KEY), // the_LEDG .out_port_from_the_LEDG(LEDG), // the_LEDR .out_port_from_the_LEDR(LEDR), // the_SEG7 .oSEG0_from_the_SEG7(HEX0), .oSEG1_from_the_SEG7(HEX1), .oSEG2_from_the_SEG7(HEX2), .oSEG3_from_the_SEG7(HEX3), // the_Switch .in_port_to_the_Switch(SW), // the_sdram_0 .zs_addr_from_the_sdram_0(DRAM_ADDR), .zs_ba_from_the_sdram_0({DRAM_BA_1,DRAM_BA_0}), .zs_cas_n_from_the_sdram_0(DRAM_CAS_N), .zs_cke_from_the_sdram_0(DRAM_CKE), .zs_cs_n_from_the_sdram_0(DRAM_CS_N), .zs_dq_to_and_from_the_sdram_0(DRAM_DQ), .zs_dqm_from_the_sdram_0({DRAM_UDQM,DRAM_LDQM}), .zs_ras_n_from_the_sdram_0(DRAM_RAS_N), .zs_we_n_from_the_sdram_0(DRAM_WE_N), // the_tri_state_bridge_0_avalon_slave .select_n_to_the_cfi_flash_0(FL_CE_N), .tri_state_bridge_0_address(FL_ADDR), .tri_state_bridge_0_data(FL_DQ), .tri_state_bridge_0_readn(FL_OE_N), .write_n_to_the_cfi_flash_0(FL_WE_N), // the_uart_0 .rxd_to_the_uart_0(UART_RXD), .txd_from_the_uart_0(UART_TXD), // the_sram_0 .SRAM_ADDR_from_the_sram_0(SRAM_ADDR), .SRAM_CE_N_from_the_sram_0(SRAM_CE_N), .SRAM_DQ_to_and_from_the_sram_0(SRAM_DQ), .SRAM_LB_N_from_the_sram_0(SRAM_LB_N), .SRAM_OE_N_from_the_sram_0(SRAM_OE_N), .SRAM_UB_N_from_the_sram_0(SRAM_UB_N), .SRAM_WE_N_from_the_sram_0(SRAM_WE_N), // the VGA Controller .R_from_the_vga_controller(VGA_R), .B_from_the_vga_controller(VGA_B), .G_from_the_vga_controller(VGA_G), .hsync_from_the_vga_controller(VGA_hsync), .vsync_from_the_vga_controller(VGA_vsync), /* Commented becaue don't have the lancelot Card .M1_from_the_vga_controller(VGA_M1), .M2_from_the_vga_controller(VGA_M2), .sync_n_from_the_vga_controller(VGA_sync_n), .sync_t_from_the_vga_controller(VGA_sync_t), .vga_clk_to_the_vga_controller(VGA_vga_clk), .blank_n_from_the_vga_controller(VGA_blank), */ );
And please uncomment this section:system_0 u0 ( // 1) global signals: .clk(CPU_CLK), .reset_n(CPU_RESET), // the_KEY .in_port_to_the_KEY(KEY), // the_LEDG .out_port_from_the_LEDG(LEDG), // the_LEDR .out_port_from_the_LEDR(LEDR), // the_SEG7 .oSEG0_from_the_SEG7(HEX0), .oSEG1_from_the_SEG7(HEX1), .oSEG2_from_the_SEG7(HEX2), .oSEG3_from_the_SEG7(HEX3), // the_Switch .in_port_to_the_Switch(SW), // the_sdram_0 .zs_addr_from_the_sdram_0(DRAM_ADDR), .zs_ba_from_the_sdram_0({DRAM_BA_1,DRAM_BA_0}), .zs_cas_n_from_the_sdram_0(DRAM_CAS_N), .zs_cke_from_the_sdram_0(DRAM_CKE), .zs_cs_n_from_the_sdram_0(DRAM_CS_N), .zs_dq_to_and_from_the_sdram_0(DRAM_DQ), .zs_dqm_from_the_sdram_0({DRAM_UDQM,DRAM_LDQM}), .zs_ras_n_from_the_sdram_0(DRAM_RAS_N), .zs_we_n_from_the_sdram_0(DRAM_WE_N), // the_tri_state_bridge_0_avalon_slave .select_n_to_the_cfi_flash_0(FL_CE_N), .tri_state_bridge_0_address(FL_ADDR), .tri_state_bridge_0_data(FL_DQ), .tri_state_bridge_0_readn(FL_OE_N), .write_n_to_the_cfi_flash_0(FL_WE_N), // the_uart_0 .rxd_to_the_uart_0(UART_RXD), .txd_from_the_uart_0(UART_TXD), // the_sram_0 .SRAM_ADDR_from_the_sram_0(SRAM_ADDR), .SRAM_CE_N_from_the_sram_0(SRAM_CE_N), .SRAM_DQ_to_and_from_the_sram_0(SRAM_DQ), .SRAM_LB_N_from_the_sram_0(SRAM_LB_N), .SRAM_OE_N_from_the_sram_0(SRAM_OE_N), .SRAM_UB_N_from_the_sram_0(SRAM_UB_N), .SRAM_WE_N_from_the_sram_0(SRAM_WE_N), // the VGA Controller .R_from_the_vga_controller(VGA_R), .B_from_the_vga_controller(VGA_B), .G_from_the_vga_controller(VGA_G), //HERE IS WHERE YOU WENT WRONG .hsync_from_the_vga_controller(VGA_HS), .vsync_from_the_vga_controller(VGA_VS), .M1_from_the_vga_controller(VGA_M1), .M2_from_the_vga_controller(VGA_M2), .sync_n_from_the_vga_controller(VGA_SYNC_N), .sync_t_from_the_vga_controller(VGA_SYNC_T), .vga_clk_to_the_vga_controller(VGA_VGA_CLK), .blank_n_from_the_vga_controller(VGA_BLANK) );
VGA needs to have these parameters./*Commented becaue don't have the lancelot Card output VGA_CLK; // VGA Clock output VGA_BLANK; // VGA Blank output VGA_SYNC_N; // VGA Sync output VGA_SYNC_T; // VGA Sync output VGA_M1; // VGA M1 output VGA_M2; // VGA M2- Altera_Forum
Ok i have write your modification.
Thanks you very much ! Compilation works and in the pin planner some new nodes appear. But nothing more with monitor. Here is my actual project including the software part: http://sega4ever.power-heberg.com/fpga/de1_nios.rar I think he should not miss much thing now :cool: - Altera_Forum
I made a typo. Shouldn't be "VGA_VGA_CLK", it should be "VGA_CLK" according to your input and output declarations (which I keep telling you to look at). You can't name the signals anything you want and expect it to work!
Also, you need to connect the net VGA_CLK to a clock. The frequency depends on your resolution. If it's 640x480 vga, use a 25Mhz clock. If 800x600 use 40 MHz. So what you need to do is the following: 1. Create a PLL from Megawizard (ALTPLL) and create a 40 MHz or 25 Mhz clock. It should take an input clock (inclk0) of 50Mhz and an output clock (c0) of 25 Mhz or 40 Mhz. Name it vga_pll and add it to project. If you don't know how to do this look at the documentation. 2. Add this code to DE1_NIOS.v:
Also, please refer to this tutorial: http://www.asic-world.com/verilog/veritut.html What I just told you is very basic Verilog.vga_pll pll1 ( .inclk0(CLOCK_50), .c0(VGA_CLK) //25 or 40 Mhz ); - Altera_Forum
Thanks!
I already have a PLL with the "inclk0(CLOCK_50)"
So i have made c2 in 40Mhz and writted this:SDRAM_PLL PLL1 (.inclk0(CLOCK_50),.c0(DRAM_CLK),.c1(CPU_CLK));
Compilation seems to works but with no change. did you want my project ?SDRAM_PLL PLL1 (.inclk0(CLOCK_50),.c0(DRAM_CLK),.c1(CPU_CLK),.c2(VGA_CLK)); - Altera_Forum
HI,
Did someone could help me please ? i have integrated the VGA_Controller in SOPC Builder and wire the pins , but vga seems not be initialized when i flash my .sof.
