Forum Discussion
Altera_Forum
Honored Contributor
14 years agoI made a typo. Shouldn't be "VGA_VGA_CLK", it should be "VGA_CLK" according to your input and output declarations (which I keep telling you to look at). You can't name the signals anything you want and expect it to work!
Also, you need to connect the net VGA_CLK to a clock. The frequency depends on your resolution. If it's 640x480 vga, use a 25Mhz clock. If 800x600 use 40 MHz. So what you need to do is the following: 1. Create a PLL from Megawizard (ALTPLL) and create a 40 MHz or 25 Mhz clock. It should take an input clock (inclk0) of 50Mhz and an output clock (c0) of 25 Mhz or 40 Mhz. Name it vga_pll and add it to project. If you don't know how to do this look at the documentation. 2. Add this code to DE1_NIOS.v:
vga_pll pll1 ( .inclk0(CLOCK_50),
.c0(VGA_CLK) //25 or 40 Mhz
);
Also, please refer to this tutorial: http://www.asic-world.com/verilog/veritut.html What I just told you is very basic Verilog.