Forum Discussion
Altera_Forum
Honored Contributor
14 years agoThanks!
I already have a PLL with the "inclk0(CLOCK_50)"
SDRAM_PLL PLL1 (.inclk0(CLOCK_50),.c0(DRAM_CLK),.c1(CPU_CLK));
So i have made c2 in 40Mhz and writted this:
SDRAM_PLL PLL1 (.inclk0(CLOCK_50),.c0(DRAM_CLK),.c1(CPU_CLK),.c2(VGA_CLK));
Compilation seems to works but with no change. did you want my project ?