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Altera_Forum
Honored Contributor
Honored ContributorStarting point for DE1 Board
Hi all, Recently i have buy the Altera DE1 Board. My objectif is to make a projects with Nios II F and all the things with a commented source for everyone want to start a project with DE1 and...
Altera_ForumHonored Contributor
Honored Contributor1. Those are syntax errors. You might have deleted a ")".
2. Please use the name of the outputs declared in your top module. That means, not "VGA_hsync", but it should be "VGA_HS", because that was how it's declared in the top module. Using "VGA_hsync" just creates a net that doesn't connect anywhere. 3. Remember that in verilog everything is case sensitive. "VGA" is not the same as "vga" or "Vga". I suggest you refer to a Verilog tutorial ASAP.
