Forum Discussion
Altera_Forum
Honored Contributor
14 years agoNo actually you don't understand at all.
Here's what I mean. In the .rar file you've supplied, you did this: // the VGA Controller
.R_from_the_vga_controller(R),
.B_from_the_vga_controller(B),
.G_from_the_vga_controller(G),
what it should be is this: // the VGA Controller
.R_from_the_vga_controller(VGA_R),
.B_from_the_vga_controller(VGA_B),
.G_from_the_vga_controller(VGA_G),
since those are the names of the outputs you have declared. I suggest you try to understand Verilog. What your problem was, is that the outputs of your top level module VGA_R, VGA_B, VGA_G, VGA_HSYNC_N, etc. are assigned physically to VGA, but nothing in your Verilog actually drives these signals, therefore there can't be any signal.