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Altera_Forum
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16 years ago

SSRAM Verify failed after adding custom components in SOPC Builder

I created a system based on the template for the Stratix II Nios Kit. I took the SDRAM away since I don't have a license for that IP Core. I intended to use SSRAM since it's a small project. I compiled in quartus and programmed the FPGA then created a hello world application in Nios IDE and it compiled and run ok. Now when I add custom components in SOPC Builder like PWM and ADC interface, generate, assign pins, compile in quartus, and try to compile in Nios IDE I get verify failed at address 0x01000000.

I configured unused pins as tristate inputs and triple check pins assignments so I don't know what could be the problem. Can anyone help me please?

15 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Did you constrain the memory interface and does your design meet the timing requirements when you compile it?

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    Altera_Forum
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    14 years ago

    hi i have the same problem i'm using an ssram in my design at STRatix II and the rpject compiled successufilly but when i use the NIOS IDE with the project of hello world the project build with no error but when i run it i have this problem

    Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

    Pausing target processor: OK

    Reading System ID at address 0x00801040: verified

    Initializing CPU cache (if present)

    OK

    Downloading 00400000 ( 0%)

    Downloaded 53KB in 0.9s (58.8KB/s)

    Verifying 00400000 ( 0%)

    Verify failed between address 0x400000 and 0x40D073

    Leaving target processor paused

    plz some one can help me
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Did you constrain the memory interface and does your design meet the timing requirements when you compile it?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    what do u mean by memory interface and yes when i compile i have timing requirements

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    By memory interface I mean the FPGA pins that are connected to the memory. You should check that your timing contraints file is correct on those signals.