Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

SSRAM Verify failed after adding custom components in SOPC Builder

I created a system based on the template for the Stratix II Nios Kit. I took the SDRAM away since I don't have a license for that IP Core. I intended to use SSRAM since it's a small project. I compil...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

By memory interface I mean the FPGA pins that are connected to the memory. You should check that your timing contraints file is correct on those signals.