Hi, I'm trying to get handle with the SPI on a Nios II Core but I don't get it. I have a SPI master and a SPI Slave that I can try to transmit some data from the master to the slave. I connected them with the "loopback board". My Code is: //Write some data to the Slave IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(SPI_SLAVE_BASE,0x04); //Check the TRDY bit if data is written(TRDY=0 means it is writing and //TRDY=1 again means the data was written) trdyNumber=(IORD_ALTERA_AVALON_SPI_STATUS(SPI_SLAVE_BASE)& ALTERA_AVALON_SPI_STATUS_TRDY_MSK)>>6; //Read from the register int data=(IORD_ALTERA_AVALON_SPI_RXDATA(SPI_SLAVE_BASE)&0xFF); printf("%d",data); I also read the manuel for the SPI Core but it doesn't work. Can somebody help my with an exsample or give me an advice? Regards

Your code contains several mistakes: IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(SPI_SLAVE_BASE,0x04) This doesn't write data to the slave, but it selects (enables) slave whose address is 4 for receiving data SPI slave is not supposed to transmit data autonomously. It sends data upon reception of a master request. You both send and receive data on slave. I think you meant send with master and receive with slave.

First thanks! And yes I want to send some data from Master to Slave but how? Thats what I don't understand precicely. May you can bring light in the dark.

The correct procedure is something like this: // select slave (not required in single slave system) IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(master_base, n_slave); // assert CS IOWR_ALTERA_AVALON_SPI_CONTROL(master_base, ALTERA_AVALON_SPI_CONTROL_SSO_MSK); // wait tx channel ready do { status = IORD_ALTERA_AVALON_SPI_STATUS(master_base); } while (((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0) && (status & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) == 0); // (optional) data possibly to be transmitted back from slave to master upon request IOWR_ALTERA_AVALON_SPI_TXDATA(slave_base, data_answer); // tx data IOWR_ALTERA_AVALON_SPI_TXDATA(master_base, data_tx); // this will initiate the transfer; in the same time the slave sends out on miso pin // the data ready in its tx register // Wait until the interface has finished transmitting do { status = IORD_ALTERA_AVALON_SPI_STATUS(master_base); } while ((status & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0); // release CS IOWR_ALTERA_AVALON_SPI_CONTROL(master_base, 0); // read received data from slave data_rx = IORD_ALTERA_AVALON_SPI_RXDATA(slave_base); // data_rx must match data_tx // (optional) read answer from master recvd_answer = IORD_ALTERA_AVALON_SPI_RXDATA(master_base); // recvd_answer must match data_answer Please note that I wrote this code by heart. I'm not sure this it will compile without errors.

Thanks again! I just tried your code and it is compileable but it doesen't work complitly correct. The Code looks like: --- Quote Start --- int status=0; int countTMT; // select slave (not required in single slave system) IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(SPI_MASTER_BASE, SPI_SLAVE_BASE); // assert CS IOWR_ALTERA_AVALON_SPI_CONTROL(SPI_MASTER_BASE, ALTERA_AVALON_SPI_CONTROL_SSO_MSK); // wait tx channel ready do { status = IORD_ALTERA_AVALON_SPI_STATUS(SPI_MASTER_BASE); } while (((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0) && (status & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) == 0); // (optional) data possibly to be transmitted back from slave to master upon request IOWR_ALTERA_AVALON_SPI_TXDATA(SPI_SLAVE_BASE, 0x01); // tx data IOWR_ALTERA_AVALON_SPI_TXDATA(SPI_MASTER_BASE, 0x10); // this will initiate the transfer; in the same time the slave sends out on miso pin // the data ready in its tx register // Wait until the interface has finished transmitting do{ status = IORD_ALTERA_AVALON_SPI_STATUS(SPI_MASTER_BASE); IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE,countTMT & 0x01); usleep(50000); countTMT++; } while((status & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0); // release CS IOWR_ALTERA_AVALON_SPI_CONTROL(SPI_MASTER_BASE, 0); // read received data from slave int data_rx = IORD_ALTERA_AVALON_SPI_RXDATA(SPI_SLAVE_BASE); // data_rx must match data_tx printf("Daten aus dem Slave:%d\n",data_rx); // (optional) read answer from master int recvd_answer = IORD_ALTERA_AVALON_SPI_RXDATA(SPI_MASTER_BASE); // recvd_answer must match data_answer printf("Daten aus dem Master:%d\n",recvd_answer); --- Quote End --- The result is: --- Quote Start --- Daten aus dem Slave:0 Daten aus dem Master:0 --- Quote End --- I don't understand why it doesn't work because it should. Maybe you can help me one more time. Thanks for your helt! Regards

I presume you already checked the loopback connections: - mosi output from master connected to mosi input pin to slave - miso output from slave connected to miso input to master - sclk from master feeds sclk slave input - slave select output from master drives ss input pin on slave What's your master sclk frequency? Can you test the mosi signal? Also check the status and control register on both master and slave, both before and after the execution of the above code. If you don't find anything wrong, post their values and I'll take a look. For similar spi example, you can also refer to the alt_avalon_spi_command() function in HAL driver library.

SPI Problems | Altera Community

22 Replies

Altera_Forum
Honored Contributor
14 years ago
Your ss signal is not asserted. Must be low when master is transmitting.
I see only now that you code is:
IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(SPI_MASTER_BASE, SPI_SLAVE_BASE);
That's wrong. The correct one is:
IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(SPI_MASTER_BASE, 1);
Altera_Forum
Honored Contributor
14 years ago
I think that it is not necessary to deassert ss signal when there's just one slave. It should be deasserted automatically once the transmission is started.
Altera_Forum
Honored Contributor
14 years ago
HI Cris72,

first of all thanks finally it works!
But how it is sometimes I want to know more about the SPI. So I want to know why I can't use the dummy which is transmitted from the Slave to the master as a control signal for example that the data was transmitted correct or complitly? I just recognized that the data which was written from the slave to the master as a dummy is just in the rxdata register from the master when I lode my C-Code from the NIOSII IDE the seconde time. If I when reset the system it disappear from the Master and I can just read the data from the slave.
Where does the data is which is at the second time in the rxdata register from the master at the first time? And why I'm not able to read it at the first time?
And is it possible to write some data from the slave to the master? Because I want to connect my FPGA with two uC which have to receive data from the FPGA but also have to send data to the FPGA.

I thanks in advance for your help!
Altera_Forum
Honored Contributor
14 years ago
Hi siedler.
I'm not sure I have understood your questions.
It seems you want to transmit data from the master to the slave but also from slave to master, and this is feasible.
But this is possible only upon master request. Namely, when master sends data, the slave transmits back the content of its tx register. The two data transfers (M->S and S->M) take place in the same time, on the same clock pulses, so slave tx register must be preloaded with correct data and ready to answer at the very first sclk pulse.
The slave, being a slave, can't initiate a transmission itself: it always must respond to a master request.
Altera_Forum
Honored Contributor
14 years ago
Thanks for your answer cris.
Ok I understand the circumstances. And this means for me that I need a master and a slave to send and receive data at different time.
But what is about my question, that I can just read the data which was transmitted from the slave to the master at the second time I load my C-Code to the FPGA? And how it is possible to read the dummy at the same time as the data from the slave?

Thanks in advance for you help!
Altera_Forum
Honored Contributor
14 years ago
Try changing the wait completion loop this way:

do{ IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE,countTMT & 0x01); usleep(50000); countTMT++; status = IORD_ALTERA_AVALON_SPI_STATUS(SPI_MASTER_BASE); } while( ((status & ALTERA_AVALON_SPI_STATUS_TMT_MSK) == 0) || ((status & ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0) );

Also check if timing parameters (clock polarity and phase) match master and slave.
Your problem can be possibly due to the fact that slave is missing a clock pulse, then the rx word would be completed only on the first clock pulse of next tx word, thus leading to shifted results.
Altera_Forum
Honored Contributor
14 years ago
I changed the waiting completion loop like you told me and it doesn't work. I also tried instead to wait on the TRDY-Flag to wait on the RRDY-Flag because how far I understand if the RRDY-Flag is "1" it is possible to read the register. But it also doesn't work.
I`m also checked the setup in QSYS of the both SPI Cores and till the difference that one is a master and the other one is a slave they have the same setting in relation to the clock polarity and phase. So may I change the setting for the slave or the master? Or what can I do farther?

Thanks in advance for your help!
Altera_Forum
Honored Contributor
14 years ago
Hi cris72,
me again. I recognized something which is looking quite bewildering for me. If you take a look at the picture in the attachment where you can see that in the SignalTap II the SCLK is just 25kHz and not how I set it up 128kHz. Am I wrong or where is the problem?

Thanks in advance for your help!
Altera_Forum
Honored Contributor
14 years ago
Hi I have the same problem. No matter what clock value I set up, the clock is always 64kHz. The clock polarity setting aren't working as well. I'm using Quartus II 10.1 Build 153 (and Qsys beta 10.1 build 153). Thanks for every hint!
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
Hi I have the same problem. No matter what clock value I set up, the clock is always 64kHz.
--- Quote End ---

What is the cause of this problem and what is the workaround?

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SPI Problems

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