SPI Problems

HI Cris72,

first of all thanks finally it works!

But how it is sometimes I want to know more about the SPI. So I want to know why I can't use the dummy which is transmitted from the Slave to the master as a control signal for example that the data was transmitted correct or complitly? I just recognized that the data which was written from the slave to the master as a dummy is just in the rxdata register from the master when I lode my C-Code from the NIOSII IDE the seconde time. If I when reset the system it disappear from the Master and I can just read the data from the slave.

Where does the data is which is at the second time in the rxdata register from the master at the first time? And why I'm not able to read it at the first time?

And is it possible to write some data from the slave to the master? Because I want to connect my FPGA with two uC which have to receive data from the FPGA but also have to send data to the FPGA.

I thanks in advance for your help!