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Altera_Forum's avatar
Altera_Forum
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19 years ago

SPI Bus - Shifting Bits

Hi all,

Recent reader, first time poster...

Here's the situation I am in. I am using the SPI bus of the Stratix II board to communicate with an external analog-digital converter (specifically the TLC0832). My test rig comprises a potentiometer to apply varying voltages to the Vin pin. And my test software is shown below (runs in an infinite while loop):

IOWR_ALTERA_AVALON_SPI_STATUS(SPI_BASE, 0);

IOWR_ALTERA_AVALON_SPI_SLAVE_SEL(SPI_BASE, 0xFFFF);

while ((IORD_ALTERA_AVALON_SPI_STATUS(SPI_BASE) &

ALTERA_AVALON_SPI_STATUS_TRDY_MSK) == 0)

{};

IOWR_ALTERA_AVALON_SPI_TXDATA(SPI_BASE, "Arbitrary Data");

while ((IORD_ALTERA_AVALON_SPI_STATUS(SPI_BASE) &

ALTERA_AVALON_SPI_STATUS_RRDY_MSK) == 0)

{};

printf("%d\n", (IORD_ALTERA_AVALON_SPI_RXDATA(SPI_BASE) & 0x0FF));

usleep(1000000);

Here's where things get funky. I set up 12-bit SPI data registers due to the ADC expecting 3 bits from the master, 1 bit empty and then 8 bits of actual data (hence why I mask off everything but the last 8 bits).

Now, when I run the program and read out the integer values I receive, the values jump back and forth (seemingly randomly) between 2 numbers (at different voltages, the actual numbers are different, but the jumping is still there).

Example:

7

7

56

7

56

56

7

etc... (No pattern intended)

My three sets of samples showed these pairings of numbers: 7 & 56, 14 & 115, 29 & 238. The one common linkage is that if you do a bit-shift on the larger number by 3 places to the right, you'll end up with the smaller number. (The exception to this rule is 0V, which always shows a 0 integer)

So, I was wondering whether anyone can think of what would cause a sporadic bit shift in the SPI bus? Any suggestions at all would be much appreciated.

Thanks

-Suresh

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    The SPI can be configured to sample the input at the middle of the stable input bit or at the end of the bit (this is useful for high speed communications, you get a longer settling time). But is you sample at the end you need enough hold time.

    It is possible although unlikely, that you sample the input signal in the middle between two bits, but this way you would probably get even more random results.

    Another problem may be that you generate the data from SPI to the AD with the wrong phase, so the AD recognizes the expected empty bit at the wrong position.

    A useful toll is SignalTAP, you can use it to check if the signal on the input pins is as desired. Or you can check with an external oscilloscope.

    IzI
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    If you get in there with signal tap I recommend also sampling signals like TRDY, RRDY, the shift and parallel registers, etc....

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Thanks for your help. I'll try out the SignalTap and see how that goes.

    As of right now, my assumption is that there is some sort of timing problem (such as sampling the wrong bit as a start bit or something).

    Unfortunately, I haven't had time to test out ideas because another part of the FPGA is giving me even more problems.