SPI Bus - Shifting Bits

The SPI can be configured to sample the input at the middle of the stable input bit or at the end of the bit (this is useful for high speed communications, you get a longer settling time). But is you sample at the end you need enough hold time.

It is possible although unlikely, that you sample the input signal in the middle between two bits, but this way you would probably get even more random results.

Another problem may be that you generate the data from SPI to the AD with the wrong phase, so the AD recognizes the expected empty bit at the wrong position.

A useful toll is SignalTAP, you can use it to check if the signal on the input pins is as desired. Or you can check with an external oscilloscope.

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