ciao to everybody I&#39;m trying to build a new system with cpu nios 2 , sdram ,tristate bridge and my user component I import my component vhdl file and i declare 2 port that in slave are input but in sopc i declare "writedata" . I flag on for generate header files ect At the end i click on "Generate" and sopc gerates for me my new system After i go to check in cpu_sdk the three folders -inc -lib -src Here i can find many .h and .c files , about PIO , LCD , UART but i didn&#39;t found no one file i&#39;m interesting How can i do? How can i interface my application C/C++ in Nios II IDE with my user component ? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif thanks for helps walter ciao

Walter, You&#39;re mixing two entirely different environments.... the "cpu_sdk" mode is generated _only_ when you&#39;re running in "Legacy SDK" mode and has nothing, whatsoever, to do with the IDE. There are _plenty_ of examples of components, designed for use by the Nios II IDE, however, in your <nios2_install_root>/components directory. Take a look at the altera_avalon_pio directory for a really simple example.... and move on from there... Also, you didn&#39;t mention how you&#39;re importing your VHDL code... Are you using the Component Editor? Cheers, - slacker

hi , slacker yes i know i can find examples , and i study them , as like uart , pio , led ,buttons ect But ......if i want to integrate my design After all i imported my component and integrate it in library and into system without problems , sopc generates . About my user component i know only the "base address " and the "end address" and nothing else In the examples , for examples Button_PIO i saw there are several files such as AVALON_PIO_REGS.h where are define all registers and bit to communicate . In my case , i didn&#39;t understand Sorry if i insist to understand ciao walter

Walter, I think your question is how do I write a driver for the Hal. In which case you should read Chapter 5 of the Nios II Software Developers handbook, which can be found in altera\kits\nios2\documents n2sw_nii5v2.pdf

this is a simply clock divider , and this my component i want to integrate in my system by SOPC . I added I3,I4,I5 just to see what appen in sopc builder library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity provaprogetto2 is Port( clk:in STD_LOGIC; I1:IN STD_LOGIC; I2:IN STD_LOGIC; I3:in unsigned(31 downto 0); I4:in unsigned(31 downto 0); I5:in unsigned(31 downto 0); I6:in unsigned(31 downto 0); O1:OUT STD_LOGIC; O2:OUT STD_LOGIC); end entity provaprogetto2; architecture div_clock of provaprogetto2 is signal clk_cnt : unsigned(32 downto 0); signal mem:STD_LOGIC; signal sec:unsigned(7 downto 0); signal min:unsigned(32 downto 0); begin process(clk,I2) begin if (I2=&#39;0&#39;) then clk_cnt<="000000000000000000000000000000000"; mem<=&#39;0&#39;; sec<="00000000"; min<="000000000000000000000000000000000"; O2<=&#39;1&#39;; elsif (clk=&#39;1&#39;) and (clk&#39;event) then if (clk_cnt=33000000) then clk_cnt<="000000000000000000000000000000000"; mem<=not mem; min<=min+1; if(min=2) then O2<=&#39;1&#39;; end if; else clk_cnt<=clk_cnt+1; end if; if(min=60) then O2<=&#39;0&#39;; min<="000000000000000000000000000000000"; end if; end if; end process; --O2<=I1; O1<=mem; end architecture div_clock; When i import this component , SOPC got an address memory base=0x00000800 and end=0x00000803 I declare my inputs "I1,....I5" like address or writedata , or readdata I declare different way to see what happen , ...but nothing happen I generate and SOPC told me "Ok , all generates whitout problems " Ok ,i thank , but now how can i interface my component input I1....I5 with my application IDE Nios II ? Ok i must to write header files and driver files , but wich addrress i need to use , for example for I1 (it&#39;s a bool ) where i find it ? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif I think it&#39;s difficult to explain , now i want to finish to read Quartus II Volume 4 SOPC Builder thank to everydody http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif ciao walter

The Avalon switch fabric maps all slaves bits to the lower bits of the master data , and fills any remaining upper bits with zero . The Avalon switch fabric performs simple wire-mapping in the data path but nothing else . http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif Somebody can help me ,seeing the example i wrote up , please ? I&#39;d like to sleep tonight thanks walter ciao

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13 Replies

Altera_Forum
Honored Contributor
20 years ago
now i'm trying your example
i create a new quartus 2 project, import your vhdl file and set it
as top-level , start compilation and finish good .
I open SOPC builder and import this component , and declare
the port slave like you wrote .
Add it in my system , and ready to generate .
One question :
in the SOPC builder , Avalon bus slave reserve for the component 16 word registers
base address =0x00000800
end=0x0000080F

I use only register 0 ,1,2 ,3 , but what does they means other 11 registers?
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ciao
walter
Altera_Forum
Honored Contributor
20 years ago
address width is 2
writedata width is 32 (4 Byte)

addressrange is (2^2)*4 = 16 addresses

in your case controlregister is at base address=0x00000800
reg1 (base divider) is at address=0x00000804
...

but you don't have to take this in account, if you use the MACROS
IOWR and IORD.

e.g.
IOWR(AV_CLOCK_0_BASE,CPU_CLK_DIVIDER,50000);
calculates the absolute address AV_CLOCK_0_BASE+4*CPU_CLK_DIVIDER
(in your case 0x00000800)+(4*1)=0x00000804

avalon interface is little endian

"Little Endian" means that the low-order byte of the number is stored in
memory at the lowest address, and the high-order byte at the highest address.
(The little end comes first.)

writing 32 bit (e.g. 0x12345678) into controlregister writes:
*(0x00000800)=0x78 Byte0
*(0x00000801)=0x56 Byte1
*(0x00000802)=0x34 Byte2
*(0x00000803)=0x12 Byte3

hope this helps
Altera_Forum
Honored Contributor
20 years ago
hi fisher
yes i know little endian
but i didn't understand the size of bus sizing
now i understand and i'm waiting my NIOS II kit
Next week i'll go in turchia for work and i'll try next time
thanks Fisher
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