SOPC Builder

address width is 2

writedata width is 32 (4 Byte)

addressrange is (2^2)*4 = 16 addresses

in your case controlregister is at base address=0x00000800

reg1 (base divider) is at address=0x00000804

...

but you don't have to take this in account, if you use the MACROS

IOWR and IORD.

e.g.

IOWR(AV_CLOCK_0_BASE,CPU_CLK_DIVIDER,50000);

calculates the absolute address AV_CLOCK_0_BASE+4*CPU_CLK_DIVIDER

(in your case 0x00000800)+(4*1)=0x00000804

avalon interface is little endian

"Little Endian" means that the low-order byte of the number is stored in

memory at the lowest address, and the high-order byte at the highest address.

(The little end comes first.)

writing 32 bit (e.g. 0x12345678) into controlregister writes:

*(0x00000800)=0x78 Byte0

*(0x00000801)=0x56 Byte1

*(0x00000802)=0x34 Byte2

*(0x00000803)=0x12 Byte3

hope this helps