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Altera_Forum
Honored Contributor
Honored ContributorSOPC Builder
ciao to everybody I'm trying to build a new system with cpu nios 2 , sdram ,tristate bridge and my user component I import my component vhdl file and i declare 2 port that in slave are ...
Altera_ForumHonored Contributor
Honored Contributornow i'm trying your example
i create a new quartus 2 project, import your vhdl file and set it as top-level , start compilation and finish good . I open SOPC builder and import this component , and declare the port slave like you wrote . Add it in my system , and ready to generate . One question : in the SOPC builder , Avalon bus slave reserve for the component 16 word registers base address =0x00000800 end=0x0000080F I use only register 0 ,1,2 ,3 , but what does they means other 11 registers? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif ciao walter
