SOPC Builder

Walter,

You're mixing two entirely different environments.... the "cpu_sdk" mode is generated _only_ when you're running in "Legacy SDK" mode and has nothing, whatsoever, to do with the IDE.

There are _plenty_ of examples of components, designed for use by the Nios II IDE, however, in your <nios2_install_root>/components directory. Take a look at the altera_avalon_pio directory for a really simple example.... and move on from there...

Also, you didn&#39;t mention how you&#39;re importing your VHDL code... Are you using the Component Editor?

Cheers,

- slacker

hi , slacker

yes i know i can find examples , and i study them , as like uart , pio ,

led ,buttons ect

But ......if i want to integrate my design

After all i imported my component and integrate it in library and into system without problems , sopc generates .

About my user component i know only the "base address " and the

"end address" and nothing else

In the examples , for examples Button_PIO i saw there are several files

such as AVALON_PIO_REGS.h where are define all registers and bit to

communicate .

In my case , i didn&#39;t understand

Sorry if i insist to understand

ciao

walter

Walter,

I think your question is how do I write a driver for the Hal. In which case you should read Chapter 5 of the Nios II Software Developers handbook, which can be found in altera\kits\nios2\documents n2sw_nii5v2.pdf

this is a simply clock divider , and this my component i want to

integrate in my system by SOPC .

I added I3,I4,I5 just to see what appen in sopc builder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity provaprogetto2 is

Port(

clk:in STD_LOGIC;

I1:IN STD_LOGIC;

I2:IN STD_LOGIC;

I3:in unsigned(31 downto 0);

I4:in unsigned(31 downto 0);

I5:in unsigned(31 downto 0);

I6:in unsigned(31 downto 0);

O1:OUT STD_LOGIC;

O2:OUT STD_LOGIC);

end entity provaprogetto2;

architecture div_clock of provaprogetto2 is

signal clk_cnt : unsigned(32 downto 0);

signal mem:STD_LOGIC;

signal sec:unsigned(7 downto 0);

signal min:unsigned(32 downto 0);

begin

process(clk,I2)

begin

if (I2=&#39;0&#39;) then

clk_cnt<="000000000000000000000000000000000";

mem<=&#39;0&#39;;

sec<="00000000";

min<="000000000000000000000000000000000";

O2<=&#39;1&#39;;

elsif (clk=&#39;1&#39;) and (clk&#39;event) then

if (clk_cnt=33000000) then

clk_cnt<="000000000000000000000000000000000";

mem<=not mem;

min<=min+1;

if(min=2) then

O2<=&#39;1&#39;;

end if;

else clk_cnt<=clk_cnt+1;

end if;

if(min=60) then

O2<=&#39;0&#39;;

min<="000000000000000000000000000000000";

end if;

end if;

end process;

--O2<=I1;

O1<=mem;

end architecture div_clock;

When i import this component , SOPC got an address memory

base=0x00000800 and end=0x00000803

I declare my inputs "I1,....I5" like address or writedata , or readdata

I declare different way to see what happen , ...but nothing happen

I generate and SOPC told me "Ok , all generates whitout problems "

Ok ,i thank , but now how can i interface my component input I1....I5 with my application IDE Nios II ?

Ok i must to write header files and driver files , but wich addrress i need to use , for example for I1 (it&#39;s a bool ) where i find it ?

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

I think it&#39;s difficult to explain , now i want to finish to read Quartus II

Volume 4 SOPC Builder

thank to everydody http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

ciao

walter

The Avalon switch fabric maps all slaves bits to the lower bits of the master data , and fills any remaining upper bits with zero .

The Avalon switch fabric performs simple wire-mapping in the data path

but nothing else .

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

Somebody can help me ,seeing the example i wrote up , please ?

I&#39;d like to sleep tonight

thanks

walter

ciao

SOPC builder generate MySystem and all files .

The file i think most importat is the "class.ptf" that describe my system

including my component .

Here i can see my declarations , like as i wrote up , in the preview post .

PORT_WIRING

{

PORT clk

{

width = "1";

direction = "input";

type = "clk";

}

PORT i1

{

width = "1";

direction = "input";

type = "reset";

}

PORT i2

{

width = "1";

direction = "input";

type = "write";

}

PORT i3

{

width = "32";

direction = "input";

type = "writedata";

}

PORT i4

{

width = "32";

direction = "input";

type = "writedata";

}

PORT i5

{

width = "32";

direction = "input";

type = "writedata";

}

PORT i6

{

width = "32";

direction = "input";

type = "address";

}

PORT o1

{

width = "1";

direction = "output";

type = "export";

}

PORT o2

{

width = "1";

direction = "export";

type = "";

}

}

}

SIMULATION

{

DISPLAY

{

SIGNAL a

{

name = "clk";

}

SIGNAL b

{

name = "i1";

}

SIGNAL c

{

name = "i2";

}

SIGNAL d

{

name = "i3";

radix = "hexadecimal";

}

SIGNAL e

{

name = "i4";

radix = "hexadecimal";

}

SIGNAL f

{

name = "i5";

radix = "hexadecimal";

}

SIGNAL g

{

name = "i6";

radix = "hexadecimal";

}

SIGNAL h

{

name = "o1";

}

SIGNAL i

{

name = "o2";

}

}

}

}

Ok now the system knows my component.

How may i write the low-level library to enter and interface it with

Nios II IDE ?

Don&#39;t fight me , be patient

It&#39;s only ten days i&#39;m starting with altera fpga and this world

thanks

walter

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif

thanks fisher

now i want to study your program

ciao

walter

for examples , i don&#39;t know when , but in the future i wish to create a user

custom component that read and write external digital I/O

My component will have output pins (8 for databits , 4 for address bit )

and like as a parallel bus , it reads data from other electronics cards

like as an data acquisitions system .

I want to read 32 + 32 +32 +32 input and write 32 +32 +32 +32 +32 output digital I/O.

In my component , i suppose i must to provide a multiplexer that read

this data from external system , and after i want to "send" this data to the

NIOS II processor

The custom componet avalon bus said i can to use 4 word register .

One of these registers is the address and the other one is data (read o write 32 bits) .

In this case i must to declare in my system N component (Ndatabits /32 ) or i can to declare just one and work with register address in avalon bus?

From documents i saw that every user component has 4 word 32 bits register , but i don&#39;t understand wich is the address , wich is writedata , wich is the chipselect (may be this one is automatically generate by Avalon bus)

I&#39;m reading fisher&#39;s examples and also pwm axamples from Altera

I studied several tutor and manuals , but sorry http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif i never understand

this concepts very well

So i&#39;m not sure to understand good

It&#39;s very embarrassing situation , mine situation and i don&#39;t want to

make noises to everybody .

ciao

walter

now i understand all

Thanks Fisher

One question , in your example i saw :

# define CONTROL_REGISTER 0# define STATUS_REGISTER 0# define CPU_CLK_DIVIDER 1# define ALARM_TIME_REGISTER 2# define ACTUAL_TIME_REGISTER 3

these are the register

the first one in writing mode and reading mode is the control/status register

of avalon interfrace .

the others ones are in order the register you use in your component.

Then in your component analyze wich address and respond or read about your necessity.

for example in this case

IOWR(AV_CLOCK_0_BASE,CPU_CLK_DIVIDER,50000)

the parameters macro&#39;s are :

AV_CLOCK_0_BASE the address base defined in SOPC Builder

CPU_CLK_DIVIDER the offset ralative the address base

50000 the writedata value

Avalon bus read the address and multipexs and generate automatically

chipselect ...

So , if i what to have other register to interface with Avalon bus

i must to increase the widht of address in the table in SOPC builder when i import my component and then declare this registers in my component .

In your case you declare address widht =2 (00,01,10,11) and the multiplexer cases are 4

The address offset is likes the index "i" in an array that points to exact register i choose.

If i declare address widht=3 (000,0010....1111) i can to use 8 register

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

Now i like this system and to continue studing .

thanks Fisher

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif