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Altera_Forum
Honored Contributor
Honored ContributorSOPC Builder
ciao to everybody I'm trying to build a new system with cpu nios 2 , sdram ,tristate bridge and my user component I import my component vhdl file and i declare 2 port that in slave are ...
Altera_ForumHonored Contributor
Honored ContributorWalter,
You're mixing two entirely different environments.... the "cpu_sdk" mode is generated _only_ when you're running in "Legacy SDK" mode and has nothing, whatsoever, to do with the IDE. There are _plenty_ of examples of components, designed for use by the Nios II IDE, however, in your <nios2_install_root>/components directory. Take a look at the altera_avalon_pio directory for a really simple example.... and move on from there... Also, you didn't mention how you're importing your VHDL code... Are you using the Component Editor? Cheers, - slacker
