SOPC Builder

Honored Contributor

20 years ago

now i understand all

Thanks Fisher

One question , in your example i saw :

# define CONTROL_REGISTER 0# define STATUS_REGISTER 0# define CPU_CLK_DIVIDER 1# define ALARM_TIME_REGISTER 2# define ACTUAL_TIME_REGISTER 3

these are the register

the first one in writing mode and reading mode is the control/status register

of avalon interfrace .

the others ones are in order the register you use in your component.

Then in your component analyze wich address and respond or read about your necessity.

for example in this case

IOWR(AV_CLOCK_0_BASE,CPU_CLK_DIVIDER,50000)

the parameters macro's are :

AV_CLOCK_0_BASE the address base defined in SOPC Builder

CPU_CLK_DIVIDER the offset ralative the address base

50000 the writedata value

Avalon bus read the address and multipexs and generate automatically

chipselect ...

So , if i what to have other register to interface with Avalon bus

i must to increase the widht of address in the table in SOPC builder when i import my component and then declare this registers in my component .

In your case you declare address widht =2 (00,01,10,11) and the multiplexer cases are 4

The address offset is likes the index "i" in an array that points to exact register i choose.

If i declare address widht=3 (000,0010....1111) i can to use 8 register

Now i like this system and to continue studing .

thanks Fisher

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