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Altera_Forum's avatar
Altera_Forum
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16 years ago

Slow DDR access.

Hi Guys, We are using Nios II with a DDR HP Controller in full-rate, both at 100MHz on Cyclone III. The design is an SOPC builder with Avalon-MM interface. Our DDR Memory is a single device 16b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Don't panic! :-)

In component editor you should declare external_sys_clk as "conduit_end"-Interface with "export"-Signal Type.

In .tcl file you then see somethink like that:

add_interface_port conduit_end external_sys_clk export Output 1

That's all!

Regards,

Kest