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Altera_Forum's avatar
Altera_Forum
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16 years ago

Slow DDR access.

Hi Guys, We are using Nios II with a DDR HP Controller in full-rate, both at 100MHz on Cyclone III. The design is an SOPC builder with Avalon-MM interface. Our DDR Memory is a single device 16b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I've done this before but I think it is a bad style:

Just write a AVLON-Slave component with nothing else but:

external_sys_clk <= DDR_Controller_sysclk;

Maybe the is a better way to do this?

Kest