Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Slow DDR access.

Hi Guys, We are using Nios II with a DDR HP Controller in full-rate, both at 100MHz on Cyclone III. The design is an SOPC builder with Avalon-MM interface. Our DDR Memory is a single device 16b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks Kest, jakobjones and dsl

I'm trying to implement your suggestion, selecting the DDR_Controller_sysclk for all SOPC devices but we need the clock also outside the SOPC block for synchronous logic. How can we transfer the DDR_Controller_sysclk instead of the regular sysCLK?? Maybe you have an idea??

Thanks and bye.