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Altera_Forum
Honored Contributor
Honored ContributorSlow DDR access.
Hi Guys, We are using Nios II with a DDR HP Controller in full-rate, both at 100MHz on Cyclone III. The design is an SOPC builder with Avalon-MM interface. Our DDR Memory is a single device 16b...
Altera_ForumHonored Contributor
Honored ContributorIt is rather a PITA that the SoPC builder just adds clock crossing logic (and bus width logic) without telling you - or requiring a box ticked.
It is very easy to gets these things added when you don't really need/want them. Does the SDRAM interface work the same way? Or is that run from the normal sysclk itself? Some of my experiments seem to imply that the sdram interface will 'post' two write cycles.
