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Altera_Forum
Honored Contributor
Honored ContributorSlow DDR access.
Hi Guys, We are using Nios II with a DDR HP Controller in full-rate, both at 100MHz on Cyclone III. The design is an SOPC builder with Avalon-MM interface. Our DDR Memory is a single device 16b...
Altera_ForumHonored Contributor
Honored ContributorNice catch Kest.
He's right. You should be using the "DDR_Controller_sysclk" as the clock for everything else. Otherwise SoPC builder will automatically insert clock crossing logic which will most certainly increase latency. Jake
