Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSlow DDR access.
Hi Guys, We are using Nios II with a DDR HP Controller in full-rate, both at 100MHz on Cyclone III. The design is an SOPC builder with Avalon-MM interface. Our DDR Memory is a single device 16b...
Altera_ForumHonored Contributor
Honored ContributorJust a quick reply:
Your DDR_Controller has SysCLK as a master clock and a DDR_Controller_sysclk as a generated clock. Both are 100 MHz _but_ you have to use DDR_Controller_sysclk as you master clock (instead of SysCLK) for DMA Controller/NIOS or something else. Otherwise you have waitstates, just like you describe it above! Kest
