Simulating NIOS2 core in modelsim(newbie question)

Hi there,

I just got NIOS2 and I am trying to get a simulation of the standard example working in Modelsim. When I try to run the simulation I get this message:

# ************************************************************# This testbench includes an SOPC Builder Generated Altera model:# 'sdram_test_component.vhd', to simulate accesses to SDRAM.# Initial contents are loaded from the file: 'sdram.dat'.# ************************************************************# ** Fatal: (vsim-3710) Qualified expression type mark slv4 constraint 1 to 4 is not same as operand constraint 5 to 8.# Time: 63 ns Iteration: 1 Process: /test_bench/dut/the_cpu/nll0ioii/line__768 File: C:/altera/kits/full/cpu_test_bench.vhd# Fatal error at C:/altera/kits/full/altera_vhdl_support.vhd line 451

the code it is refering to is automaticly generated and as far as I can see just tries to get rid of the zeros. All I did was generate a standard CPU with modelsim support from the standard example, start NIOS2 IDE, make a hello world project, run it as modelsim program. In modelsim it automaticly sets up and I just use the s and w commands to start the simulation, but when I run it it gives me the error above after 60ns.

I followed this document http://www.altera.com/literature/an/an351.pdf (http://www.altera.com/literature/an/an351.pdf)

I used only premade things, so why is it going wrong?

Hope you have an answer.

Regards,

David

BTW, I am using Quartus II 4.1 and Modelsim SE PLUS 6.0a