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Altera_Forum
Honored Contributor
Honored ContributorSimulating NIOS II with ModelSim
When compiling NIOS II with ModelSim, I got the following errors:
( I used the "full featured version" provided with V7 distribution).# -- Compiling entity cpu# -- Compiling architecture rtl of cpu# ** Error: C:/altera/70/nios2eds/examples/vhdl/niosII_stratixII_2s60_ES/full_featured/cpu.vho(13879): (vcom-1136) Unknown identifier "clock_enable_core_a".# ** Error: C:/altera/70/nios2eds/examples/vhdl/niosII_stratixII_2s60_ES/full_featured/cpu.vho(13880): (vcom-1136) Unknown identifier "clock_enable_core_b".# ** Error: C:/altera/70/nios2eds/examples/vhdl/niosII_stratixII_2s60_ES/full_featured/cpu.vho(13885): (vcom-1136) Unknown identifier "enable_ecc".# ** Error: C:/altera/70/nios2eds/examples/vhdl/niosII_stratixII_2s60_ES/full_featured/cpu.vho(13903): (vcom-1136) Unknown identifier "read_during_write_mode_port_a".# ** Error: C:/altera/70/nios2eds/examples/vhdl/niosII_stratixII_2s60_ES/full_featured/cpu.vho(13904): (vcom-1136) Unknown identifier "read_during_write_mode_port_b". etc... # ** Error: C:/altera/70/nios2eds/examples/vhdl/niosII_stratixII_2s60_ES/full_featured/cpu.vho(34208): VHDL Compiler exiting# c:/modeltech_ae/win32aloem/vcom failed. Did anybody get these errors? Any idea to fix the errors? Thanks de8 Replies
Altera_ForumHi,
Not as familar with the VHDL flow of Modelsim/Nios. Looks like your VCOM error does not see a node or something. Just a guess, maybe a -novopt command may help. -Baycool- Altera_Forum
Do you have any warning or errors during synthesis with quartus?
Most of the time quartus detects all the mistakes in your vhdl/verilog.... - Altera_Forum--- Quote Start --- originally posted by romain53@Mar 27 2007, 09:48 AM do you have any warning or errors during synthesis with quartus?
most of the time quartus detects all the mistakes in your vhdl/verilog....
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--- Quote End --- As shown in the path, the compilation errors occur when ModelSim compiles the VHDL version of the CPU provided by Altera. I didn't write any VHDL code. There is neither errors nor warning when compiling the system with Quartus. I was wondering if the errors come from the system (generated by SoC builder) or from the VHDL version of the CPU that is OK for Quartus, but actually not for ModelSim. de
- Altera_Forum
Are you using the supplied tcl script?
- Altera_Forum--- Quote Start --- originally posted by tembridis@Mar 27 2007, 11:10 AM are you using the supplied tcl script?
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--- Quote End --- I am following the procedure of application note 351: simulating Nios II embedded processor designs. ModelSim is launched from NIOSII IDE. Then I use the "s" command. de
- Altera_Forum
Hi de,
As a sanity check compile a trival design( A Nios , JTAG UART and Memory with a simple Hello World) and see what you get. If you are following the flow in AN351 you should have no problems. -Baycool - Altera_Forum--- Quote Start --- originally posted by baycool@Mar 27 2007, 07:07 PM hi de,
as a sanity check compile a trival design( a nios , jtag uart and memory with a simple hello world) and see what you get. if you are following the flow in an351 you should have no problems.
-baycool
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--- Quote End --- This is exactly what I have done and I have got... the compiler errors. de
- Altera_Forum
Problem is solved.
With Quartus II version 7.0, the latest version of ModelSIM (6.1.g) is needed. de
