Simulating NIOS II with ModelSim

--- Quote Start ---

originally posted by romain53@Mar 27 2007, 09:48 AM

do you have any warning or errors during synthesis with quartus?

most of the time quartus detects all the mistakes in your vhdl/verilog....

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=22536)

--- quote end ---

--- Quote End ---

As shown in the path, the compilation errors occur when ModelSim compiles the VHDL version of the CPU provided by Altera. I didn&#39;t write any VHDL code.

There is neither errors nor warning when compiling the system with Quartus.

I was wondering if the errors come from the system (generated by SoC builder) or from the VHDL version of the CPU that is OK for Quartus, but actually not for ModelSim.

de