Shared memory between hardware and uClinux

IMHO, you in fact should create an Avalon bus master module (aka DMA) that reads memory data words from memory and writes them to the DACs.

Why do you think that there is a problem with external memory ? Your Module just accesses the Avalon bus with the appropriate address. AFAIK the Avalon bus design automatically handles bus conflicts.

You need to take care that the shared memory region is accessed with the CPU without the cache. When doing the appropria<te Linux device driver, the system offers macros to access "DMA-Memory" for that purpose. (NIOS nommu hardware handles this very different from NIOS mmu, but the Kernel should take care of this.)

-Michael

<div class='quotetop'>QUOTE (mschnell @ Sep 9 2009, 02:21 PM) <{post_snapback}> (index.php?act=findpost&pid=23795)</div>

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IMHO, you in fact should create an Avalon bus master module (aka DMA) that reads memory data words from memory and writes them to the DACs.

Why do you think that there is a problem with external memory ? Your Module just accesses the Avalon bus with the appropriate address. AFAIK the Avalon bus design automatically handles bus conflicts.

You need to take care that the shared memory region is accessed with the CPU without the cache. When doing the appropria<te Linux device driver, the system offers macros to access "DMA-Memory" for that purpose. (NIOS nommu hardware handles this very different from NIOS mmu, but the Kernel should take care of this.)

-Michael[/b]

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Thanks for your reply,

The avalon bus cannot be accessed from hardware though it? When i say hardware I mean HDL? We need hardware to write to the DACS. I don&#39;t think DMA will do the trick because we need to manipulate the data in hardware before writting to the DACS.

Basically, the application transits different wave forms, sort of like a signal generator. The PC will send this data which may be up to 600kb and the hardware will need to output this data at 10Khz.

<div class='quotetop'>QUOTE (Gaz @ Sep 9 2009, 04:15 PM) <{post_snapback}> (index.php?act=findpost&pid=23796)</div>

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The avalon bus cannot be accessed from hardware though it? When i say hardware I mean HDL?[/b]

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I don&#39;t see what you mean by this. Of course you can create a "hardware" component that actively accesses slave-components via the Avalon bus (e.g. a DMA controller).

<div class='quotetop'>QUOTE (Gaz @ Sep 9 2009, 04:15 PM) <{post_snapback}> (index.php?act=findpost&pid=23796)</div>

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We need hardware to write to the DACS. I don&#39;t think DMA will do the trick because we need to manipulate the data in hardware before writting to the DACS.[/b]

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The Avalon master interface of your component would read the data from memory, your hardware does the "manipulation" and writes it to the DACs.

<div class='quotetop'>QUOTE (Gaz @ Sep 9 2009, 04:15 PM) <{post_snapback}> (index.php?act=findpost&pid=23796)</div>

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Basically, the application transits different wave forms, sort of like a signal generator. The PC will send this data which may be up to 600kb and the hardware will need to output this data at 10Khz.[/b]

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What do you mean by "The PC will send this data" ? I suppose via some standard interface (serial, USB, Ethernet...). So I suppose you need some kind of FIFO or "repetition storage" between the input from the PC interface and the output to the DACs. This can be done as a "hardware" FIFO the NIOS writes to via the Avalon bus (so your component that includes the FIFO and the interface to the DACs will have an Avalon slave interface), or the CPU writes the data into a normal memory and your component will actively read the data from memory (so your component that has the interface to the DACs will have an Avalon master interface to do that, supposedly plus an Avalon slave interface to exchange command and status informations with the NIOS).

-Michael