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Altera_Forum's avatar
Altera_Forum
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16 years ago

seperate memories for data and instruction masters?

I'm curious if anyone has experimented with putting 2 on chip memories in an SOPC. One which is connected to the nios instruction master and one that is connected to the data master? It seems there could be some bottleneck with a single memory hooked to both masters. Both masters will be being arbitrated if they share a common on chip memory.

Also I'm curious which parts of the C code are exclusive to which master.

Meaning

which bus accesses instruction code (.text)

which bus accesses read-only data mem (.rodata)

which bus accesses r/w data mem (.rwdata)

which bus accesses the heap

which bus accesses the stack.

Are each of these sections accesses by only one master or are some of them shared by both the data and instruction masters?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The instruction master will only read instructions! For a normal compilation this is all that is in .text.

    Everything else is read by the data master - including the .rodata that contains the jump tables for some switch statements.

    So you may want to arrange that the linker puts .rodata in the data memory, not with the .text.

    Then you technically don't need data access from the nios cou to the instruction memory. But ...

    The linker may also be placing the initialised data immediately after the .text and adding code to copy it to the relevant areas. This will require read (data) access to the code memory. Or use a different linker script etc.

    You also need to be able to get your code into the instruction memory!

    The JTAG loader writes everything from the Nios cpu - so needs write access to the code memory.

    If you are loading from some external interface (eg PCIe) then the external interface needs MM-Avalon bus access to both the code and data memory block. The nios cpu doesn't need MM access to the data area - so it can have the same address for both masters.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    could there be any advantage to using a dual port on chip RAM hooked to the CPU. Instruction master hooked to one port and the data master hooked to the other port. There must be some tradeoff here. Maybe it just takes more logic to implement but will give better performance?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    If you don't need any other master access to the memory, that should be ok.

    The M9K memory blocks used for on-chip memory are desgined as dual-ported.

    It will be significantly faster than using the data and instruction caches.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    you would think altera would be pushing this approach or at least mentioning it in their documentation. Maybe this is where tightly coupled memories come into play. I have read through their optimization doc and they never mention putting seperate on chip mems for data and instructions. And tightly coupled memory sounds like a pain since you have to be explicit about which functions get put into the fast section....