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Altera_Forum's avatar
Altera_Forum
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16 years ago

seperate memories for data and instruction masters?

I'm curious if anyone has experimented with putting 2 on chip memories in an SOPC. One which is connected to the nios instruction master and one that is connected to the data master? It seems there ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

If you don't need any other master access to the memory, that should be ok.

The M9K memory blocks used for on-chip memory are desgined as dual-ported.

It will be significantly faster than using the data and instruction caches.