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Altera_Forum's avatar
Altera_Forum
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21 years ago

Selective Cache Enable/Disable support

Hi,

Does NIOSII processor support selective caching of the entire system-address space.

For example in system address space we have the SDRAM, and all other addressable-peripherals. Whenever any peripheral region is addressed by registers the s/w does not expect processor to read data from cache instead directly from regs for latest update.

And in Linux we use the request_io_region() with cache support disabled for those memory ranges, however the processor has to support cache disable for specific regions of memory right ?

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If my understanding is correct most linux drivers wont work if it would disable-cache for peripheral addressable register ? Am i Correct ?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    21 years ago

    The CPU let's the software decide on each access to memory whether it wants to bypass the D-cache or not.

    The software can either use the ldio/stio family of instructions to bypass the D-cache or can just set bit 31 of the address to 1.

    There are HAL macros to hide this from most users. I don't know what Linux provides.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    21 years ago

    the linux provides the following facilities to read/write io regs:

    inb/outb, inw/outw, inl/outl, ...

    the following to read/write device memories (bypass caches):

    readb/writeb, readw/writew, readl/writel.

    these facilities are implemented using cache bypassing instructions.

    If you want to read/write IO regions like normal ram access, you can use the 31 bit address line. Without an MMU, uClinux has no other way of bypassing cache for specific region.