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Altera_Forum
Honored Contributor
Honored ContributorSDRAM Read and write address control
Dear Friends,
i am trying to write and read data in SDRAM. but while writing and reading i don't have any control over address where i perform my read/write operation. i am using following commands for read and write operation. IOWR_ALTERA_AVALON_PIO_DATA((SDRAM_BASE),my_data) and for reading i am using IORD_ALTERA_AVALON_PIO_DATA((SDRAM_BASE) every time i run my code it start writing SDRAM from first location and while i read SDRAM it will return (again and again ) value which i write at the place where i stop writing the SDRAM. like if i write 1,2,3,4,5,6,7,8,9 and the if i read it return 9,9,9,9,9,9,9, again and again...it seems like my SDRAM read address stuch at the last address. kaushal15 Replies
Altera_Forum@daixiwen
now i can read and write at the desired offset. thanks a lot daixiwen- Altera_Forum--- Quote Start --- @ badomen how do i flush the cache?? i keep getting the wrong value... example: i wrote the offset 0 with 0x23, and then i read this offset and i get the 0x23. but then i wrote the offset 3 with 0x14 and then i read in offset 0 and i get 0x14. isn't it supposed to be 0x23?? --- Quote End --- I would attach your code to a post since any number of things could be happening. The only time I would expect the issue you are seeing is: a) When you say offset 3, if you are talking byte offset 3 and performing a 16/32 bit access then that is not allowed (unaligned access) b) You are mixing cached and non-cached accesses to the same memory location If you are doing neither then bypassing the cache shouldn't solve this problem and it's most likely something else causing the issue.
- Altera_Forum
.... oops I should read more, looks like you are up and running.
- Altera_Forum
@badomen
yeah ^__^ anyway thanks for replying... apparently i used the wrong macros - Altera_Forum
Ok just make sure to avoid# 2 from my other post. It's a common mistake that I've done myself. Typically it happens when you attempt to bypass the cache to write data to main memory using IOWR. If you also use the same memory for code (in particular stack/heap) that memory might have been previously used and cached which combined with IOWR will cause a cache coherency issue.
