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Altera_Forum's avatar
Altera_Forum
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16 years ago

SDRAM Read and write address control

Dear Friends, i am trying to write and read data in SDRAM. but while writing and reading i don't have any control over address where i perform my read/write operation. i am using following ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Ok just make sure to avoid# 2 from my other post. It's a common mistake that I've done myself. Typically it happens when you attempt to bypass the cache to write data to main memory using IOWR. If you also use the same memory for code (in particular stack/heap) that memory might have been previously used and cached which combined with IOWR will cause a cache coherency issue.