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Altera_Forum's avatar
Altera_Forum
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13 years ago

SDRAM and BSP settings

Hi everybody,

I am using the SDRAM on the DE1 board with NIOS. The bad thing is that the download of the .elf file fails without further notices. The BSP settings on the linker tab are: .bss, .heap, .stack, .rodata, .rwdata are on SDRAM. Only the .entry and .exceptions are ON-CHIP-MEMORY.

Are there special settings in BSP when using the SDRAM?

My hardware is configured with the -3ns delay on the SDRAM clock.

Thanks.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    What error message do you get when you try downloading? Nios processor not found or error during download or verification?

    Is fpga correctly configured? Does your design meet the timing?

    Usually, in such situations I suggest running a very small nios program fully contained in onchip ram, so you can test the system independently of possible sdram problems.
  • Altera_Forum's avatar
    Altera_Forum
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    I have tested the program with the ON_CHIP_MEMORY only and it's fine. I was even able to write data to the SDRAM using pointers to the address SDRAM_BASE.

    The error message I get is : Download to target fails. That's all.

    I tried different ways to mix the SDRAM and the on-chip memory but the compiler complains about the offset between the addresses which exceed 32000...
  • Altera_Forum's avatar
    Altera_Forum
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    What's your sdram clock frequency?

    Try reducing the clock phase shift to -1ns

    What do you mean the compiler complains about addresses?
  • Altera_Forum's avatar
    Altera_Forum
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    That will be the linker complaining about being unable to access some 'small data' items with offsets from %gp.

    You'll need to fix those before anything will run.

    Try loading a very small test program.
  • Altera_Forum's avatar
    Altera_Forum
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    Here is the message I get from the Nios command shell after using the command: nios2-download -g software/sw_nios2/sw_nios2.elf

    Using cable "USB-Blaster [2-1.1]", device 1, instance 0x00

    Processor is already paused

    Initializing CPU cache (if present)

    OK

    Downloaded 18KB in 0.1s

    Verifying 00800000 ( 0%)

    Verify failed between address 0x800000 and 0x803CD7

    Leaving target processor paused

    The SDRAM base address is 0x800000.

    I tried to put the clock phase shift of the SDRAM to -1ns but it does not change anything.