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Altera_Forum's avatar
Altera_Forum
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19 years ago

Running hw cmpnent at diff freq than 50 MHz

Hi everyone.

Dunno if anyone is experienced or know the solution to the problem i am having.

I have a custom hardware component which has to be run at 35 mhz

But the nios system is defaulted to run at 50 mhz.

I used the pll component to generate freq of 35 mhz to feed the custom hw component.

(By the way, I have a memory in the hw component which I also connected out to the avalon bus so I can have access to it from NIOS processor)

Anyone has experiences on running their hw component at a diff freq to the freq of their system. ?? IS there anything I should be careful about?

AND does anyone know how to solve problem on CLOCK SETUP ??

IN my compilation report, there's a -1.503.ns slack in the clock setup for my 35mhz clock. Anyone has any idea as to how to solve this problem?

My system is quite unstable now, sometimes it generates result but sometimes doesn't.

Any help is appreciated,Thank you very much in advance.

Tony

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    In Sopc builder every peripheral can have a different clock source. The Avalon bus will insert clock synchronisation logic for it automatically. Be aware of the fact that synchronisation circuitery takes a lot of wasted cycles to do its work on every read or write instruction (I think 6 cycles).

    Without this clock synchronisation, your design will not work at all.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    35MHz could be too slow for sdram, check the datasheet of the memory chips you have used. i guess you have setup the sopc for 35MHz.

    if have tried to find out how fast i could tune the pll of a nios2 inside a cyclone2 ep2c50F484I8N and i had to stop at 96MHz, the faster values that could be created out of a 48mhz clock did not fit without timing warning. But 96MHz did run perfect. no timing warnings. the sdram phase was calculated as the AN says and verified with a leCroy Scope. No over or undershot or ringing. nice to see what a fpga pin can be assigned :-)

    it is neccessary that you tune the phase of the pll if you change the pll clocks

    2 timing warnings still remain in my design with a countdone signal the sopc-pll generates but mysupport told me to forget these warnings. well i do not like warnings but i hope those guys know ....

    i have to agree that it depends if you realy need more than one clock domain. i had tried to run nios, sdram at the higher clock and all other components at a very low clock 96MHz and 8Mhz but the system performance was too bad so we deceided to run everything at the same clock speed.

    Michael Schmitt