Running hw cmpnent at diff freq than 50 MHz

35MHz could be too slow for sdram, check the datasheet of the memory chips you have used. i guess you have setup the sopc for 35MHz.

if have tried to find out how fast i could tune the pll of a nios2 inside a cyclone2 ep2c50F484I8N and i had to stop at 96MHz, the faster values that could be created out of a 48mhz clock did not fit without timing warning. But 96MHz did run perfect. no timing warnings. the sdram phase was calculated as the AN says and verified with a leCroy Scope. No over or undershot or ringing. nice to see what a fpga pin can be assigned :-)

it is neccessary that you tune the phase of the pll if you change the pll clocks

2 timing warnings still remain in my design with a countdone signal the sopc-pll generates but mysupport told me to forget these warnings. well i do not like warnings but i hope those guys know ....

i have to agree that it depends if you realy need more than one clock domain. i had tried to run nios, sdram at the higher clock and all other components at a very low clock 96MHz and 8Mhz but the system performance was too bad so we deceided to run everything at the same clock speed.

Michael Schmitt